FPGA Deployment
Deploy ATA on FPGA hardware
Resource Utilization
| Resource | Utilization | Device |
|---|
| LUTs | ~12,000 | Xilinx ZCU104 |
| FFs | ~8,000 | Xilinx ZCU104 |
| BRAM | 36 blocks | 36Kb each |
| DSP | 24 | Arithmetic |
Vivado Integration
# Add source files
add_files -fileset sources_1 [glob rtl/**/*.sv]
# Set top module
set_property top ata_top [current_fileset]
# Constraints
create_clock -period 2.857 -name clk [get_ports clk]
set_input_delay 0.5 -clock clk [all_inputs]
set_output_delay 0.5 -clock clk [all_outputs]
Software Access
#include "ata_driver.h"
// Initialize
ata_init(ATA_BASE_ADDR);
// Configure
ata_set_iter_budget(100);
ata_set_thresholds(0.25, 0.25, 0.25);
// Make decision
ata_result_t result = ata_decide_blocking(actions, n_actions);